Computer systems, e.g. Personal Computers, Workstations, Graphic Display Systems, Game Units, and a variety of other apparatuses, widely use memory components made up of, for example, DRAMs. These memory components store digital representations of information (data bits--0's and 1's) which are used by the Central Processing Unit (CPU) for processing. The rate at which the data can be stored to (written) and retrieved from (read) the DRAM accurately, i.e., access time or cycle time, is a critical parameter in computer system performance.
Most DRAMs store digital information in an array of cells, one bit per cell using a capacitor and a transistor, which are typically arranged in a two dimensional fashion, i.e. rows and columns. Rows are referred to as wordlines and columns as bitlines. A cell can be uniquely addressed by selecting its associated wordline and bitline. A DRAM supports both a read and write operation to each cell (other operations, of course, are supported but are not relevant to this invention). Both operations require a row address presented on the address input pins during a Row Address Strobe (RAS), and a column address presented on the address pins during a Column Address Strobe (CAS), thus, the memory cell is addressed for memory operations. The state of the Write Enable (WE) pin is evaluated to determine if a read or a write operation is to be performed. For a read operation, the row address is decoded by the row decoder to determine the targeted wordline and the column address is decoded by the column decoder. The selected wordline data is presented on the bitline identified by the column decoder and is connected to a primary sense amplifier that amplifies the cell data (small capacitor charge), then the bitline data is presented to a data line, which transfers the bitline data to a secondary sense amplifier, which again amplifies the data, and whose output is latched in a hold latch. This data is then processed from the hold latch to the Off Chip Driver (OCD), which presents the data to the output pins of the DRAM for processing by the computer system or by other devices.
A write operation, i.e. , WE pin enabled, parallels the read operation just described up through the step of decoding the bitline address at the CAS, which selects the memory cell. Following this, new data, stored at the data-in latch, is transferred to the write drivers which then transfer the new data to the data lines, over-write the sense amplifiers, and store the new data into the addressed cells.
There are several modes of operation such as Fast Page Mode, Pipeline Page Mode, and Extended Data Out, which are well known in the art and are not particularly relevant to the present invention. Briefly, traditional Page Mode uses the CAS leading edge to perform a memory cell access and the trailing edge to restore the access path. Extended Data Out is distinguished by data continuing to be valid after the trailing edge of CAS goes inactive and remains valid until the next leading edge of CAS. Usually, the CAS trailing edge latches the data into the hold latch, thereby allowing data to remain valid throughout the CAS restore phase.
One can improve performance of Extended Data Out by decreasing the cycle time of CAS and optimizing the associated circuitry. This approach is acceptable until the CAS (which is generated external to the memory array) cycle time becomes shorter than the time required to access data internal to the DRAM, i.e., the time for the cell potential to appear on the data line. Under this condition invalid data is processed during a read cycle since newly addressed data cannot be retrieved in time before the next CAS. Similarly, new data fails to be written accurately into the DRAM during a write cycle if the CAS active phase is too short.